1. Field of the Invention
The present invention relates to a large-scale-integration (LSI) circuit device and a method of manufacturing same, and more particularly to a delay time calculation process to be carried out in a logic simulation process in the design of LSI circuits.
2. Description of the Prior Art
As a result of semiconductor fine-circuitry fabrication technology advances in recent years, LSI circuits are experiencing larger scale integration. As a result, it is now possible to incorporate system functions in one chip. For example, a function macro which has heretofore been constructed as one chip is now incorporated together with other logic circuits in a single chip. Such a function macro includes functions of a single chip, including a CPU, multipliers, microcomputer peripherals, etc. An ordinary function macro is a relatively large circuit having a plurality of cells and memories comprise gates and flip-flops.
Many function macros standardized for the LSI circuit industry are available. The function macros include function macros uniquely designed by manufacturers of LSI circuits and function macros designed by various designing companies and sold in the market. These function macros are now a type of black box that users will find satisfactory if they perform desired functions, and are not concerned with internal structural details.
However, function macros that are available have raised a new problem in that delay time calculations cannot accurately be made in a logic simulation process required in the design of LSI circuits. Specifically, the LSI circuit fabrication procedure primarily comprises a process of designing an LSI circuit and confirming its operation through a logic simulation process, a process of designing an actual LSI mask pattern, and a process of fabricating a semiconductor wafer using the LSI mask pattern to produce LSI chips.
The logic simulation process is an indispensable process for making the process of fabricating a semiconductor wafer effective, which is highly costly to carry out. In the logic simulation process, logic operations of cells and macros in a chip are confirmed. More specifically, delay times of the cells and macros which are connected as circuits are calculated, and their logic operations are simulated and confirmed on the basis of the calculated delay times.
It is difficult to calculate the delay time of a function macro available as a black box. A function macro which is of large scale by itself has a basic internal delay time that is essentially determined when the function macro is designed. However, the delay time of an input stage of the function macro varies depending on the slew rate of a signal inputted to an input terminal of the function macro, and the delay time of an output stage of the function macro varies depending on the capacitance of a load connected to an output terminal of the function macro. These delay time variations are caused by delay times of cells depending on the slew rate of the inputted signal, the slew rate of an outputted signal, delay times of interconnections, and delay times due to different levels for deciding delay of signals, which heretofore have not been taken into account, but have to be considered due to finer circuitry schemes. The delay time variations are closely related to the fact that function macros are incorporated in chips.
If the delay time variations are accurately calculated and added to the basic internal delay time, then it is possible to accurately calculate the entire delay time of the macro in the chip. However, the input stage of a macro has a circuit configuration that differs from macro to macro, and the output stage thereof also has a circuit configuration that differs from macro to macro. Accordingly, when a logic circuit is designed using commercially available macros, it is not an easy task to calculate their delay times with accuracy.